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FPGA Development and Evaluation Board

Key dates

  1. Published

    06 Nov 2026, 10:57 AM IST

  2. Bid submission starts

    06 Nov 2026, 10:57 AM IST

  3. Bid submission ends

  4. Bids open

    28 Nov 2026, 11:00 AM IST

Eligibility and documents required

Turnover, experience and document requirements have been read from this tender's documents. Free with an account.

Work description

10 × FPGA Development and Evaluation Board (Q3) ( PAC Only )

Tender documents

  • GEM-2026-B-8240360.pdfGeM bid document

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Tender details

Tender ID
GEM/2026/B/8240360
Portal
Government e-Marketplace (GeM)
Tender type
GeM Bid
Form of contract
Total value wise evaluation
Product category
FPGA Development and Evaluation Board
Inviting authority
Malaviya National Institute Of Technology Jaipur Jawahar Lal Nehru Marg, Jaipur, Rajasthan-302017
FPGA Development and Evaluation Board | Sanganer, Jaipur, Rajasthan | FindTenders